1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly, to a semiconductor memory device having an IO compression test mode.
2. Description of the Background Art
FIG. 15 is a diagram schematically showing an entire configuration of a conventional semiconductor memory device. The semiconductor memory device MD in FIG. 15 includes: memory arrays MA0-MA3 respectively disposed for quartered regions of a chip; and row decoders RD0-RD3 provided corresponding to respective memory arrays MA0-MA3 for driving addressed rows in corresponding memory arrays MA0-MA3 to a selected state. Each of memory arrays MA0-MA3 has a storage capacity, for example, of 16M bits, and semiconductor memory device MD has a storage capacity of 64M bits, for example.
Column related circuit blocks CP0-CP3 are provided corresponding to memory arrays MA0-MA3, respectively. Each of column related circuit blocks CP0-CP3 includes: a column decoder selecting an addressed column, a preamplifier for amplifying data in a memory cell selected by the column decoder; and a write driver for writing data to the memory cell selected by the column decoder.
In a central region between memory arrays MA0, MA2 and memory arrays MA1, MA3, an internal data bus DBB is disposed common to memory arrays MA0-MA3. Internal data bus DBB has a bus width, for example, of 16 bits, and a prescribed number of data lines are used according to the pin arrangement (e.g., .times.4, .times.8 and .times.16) of semiconductor memory device MED.
In the central region between memory arrays MA0 and MA1, a peripheral pad group PPG is disposed to receive an address signal and a control signal. In the central region between memory arrays MA2 and MA3, a DQ pad group DPG is disposed for sending and receiving data to and from internal data bus DBB. Peripheral pad group PPG and DQ pad group DPG include buffering circuits provided corresponding to the pads.
In this semiconductor memory device MD, one memory array is selected in operation for data access. This is because semiconductor memory device MD takes a bank configuration, and each of memory arrays MA0-MA3 can be utilized as a bank.
FIG. 16 is a diagram schematically showing a configuration of memory array MAi (i=0-3). Memory array MAi in FIG. 16 is divided into memory cell blocks MB00-MBmn arranged in rows and columns. Memory cell blocks MB00-MBmn each have, for example, a storage capacity of 128K bits, and they are placed in eight rows and eight columns.
A sub word driver is disposed between memory cell blocks aligned in a row direction, for driving a word line of a corresponding memory cell block to a selected state. Sub word driver bands SWD1-SWDn having the sub word drivers disposed therein extend within the memory array in a column direction. Sub word driver bands SWD0 and SWDn+1 are placed outside the memory cell blocks.
In memory array MA, a hierarchical word line configuration is utilized. More specifically, a main word line is placed commonly to memory cell blocks aligned in a row direction. In the memory cell blocks, sub word lines are placed corresponding to respective rows of memory cells. Memory cells in each row in the memory cell block are connected to a corresponding sub word line. A sub word driver included in a sub word driver band drives a corresponding sub word line to a selected state according to a signal on the main word line and a predecode signal from a row decoder. This predecode signal is utilized for selecting one of a plurality of sub word lines provided corresponding to a single main word line.
Sense amplifier bands SAB1-SABm are placed between the memory cell blocks aligned in a column direction, and sense amplifier bands SAB0 and SABm+1 are placed at both sides of the memory array. Each of sense amplifier bands SAB0-SABm+1 includes: a sense amplifier circuit for sensing, amplifying and latching data of a memory cell in a corresponding column of memory cell blocks; an IO gate (column select gate) for connecting a corresponding column to an internal data transmission line according to a column select signal from the column decoder; and a bit line precharge/equalize circuit for precharging/equalizing a bit line. Each of sense amplifier bands SAB1-SABm is shared by memory cell blocks adjacent to each other in the column direction.
In memory array MA, memory cells of 16 bits are selected at one time, and the memory cells of 16 bits are coupled to corresponding preamplifier + write driver blocks via the internal data transmission lines (not shown).
FIG. 17 is a diagram schematically showing an arrangement of internal data transmission lines in the memory array shown in FIG. 16. In FIG. 17, memory cell blocks MB40-MB77 arranged in four rows and eight columns are shown. Such an array configuration as shown in FIG. 17 is disposed repeatedly in both row and column directions.
In each of sense amplifier bands SAB4-SAB8, local IO line pairs LIOP are disposed, each pair being placed corresponding to a prescribed number of memory cell blocks. In the arrangement shown in FIG. 17, in each of sense amplifier bands SAB4-SAB8, two local IO line pairs LIOP are disposed for four memory cell blocks adjacent to each other in the row direction. Each of memory cell blocks MB40-MB77 simultaneously sends and receives data to and from the local IO line pairs included in the sense amplifier bands at both sides thereof in the column direction. In the memory cell blocks along which local IO line pairs LIOP extend, memory cells of 4 bits are selected at a time.
For sub wofrd driver bands SWD0-SWD8, global IO line pairs GIOP0-GIOP7 are disposed in every other sub word driver bands SWD1, SWD3, SWD5 and SWD7 in a unit of two global IO line pairs. Local IO line pair LIOP and global IO line pair GIOP (GIOP0-GIOP7) are coupled to each other via a block select gate BSG. Block select gate BSG is driven to a selected state when memory cell blocks aligned in a row direction are selected, and couples corresponding local IO line pair LIOP and global IO line pair GIOP.
A column decoder CD is provided common to the memory cell blocks. Column decoder CD drives one column select line for four memory cell blocks adjacent to each other in the row direction, to a selected state according to a column address signal. This column select line can select memory cells of 4 bits simultaneously. Column decoder CD drives two column select lines to a selected state, and thus, memory cells of 8 bits in total are coupled to global IO line pairs GIOP0-GIOP7.
Global IO line pairs GIOP0-GIOP7 are coupled to a preamplifier + write driver block PW. In this preamplifier + write driver block PW, two global IO line pairs out of 8 bits of global IO line pairs GIOP0-GIOP7 are coupled to internal data bus DBB. In the case of a .times.4-bit configuration, this internal data bus DBB also sends and receives data of 2 bits to and fifom another preamplifier + write driver block not shown, provided for other memory blocks.
FIG. 18 is a diagram schematically showing a configuration of a portion related to one memory cell block shown in FIG. 17. Referning to FIG. 18, in each memory cell block, memory cells MC's are arranged in rows and columns, and a sub word line WL is disposed corresponding to each row of the memory cells. In FIG. 18, sub word lines WL (m-7)-WL (m+6) are shown representatively. A bit line pair is placed corresponding to each column of the memory cells. In FIG. 18, bit line pairs BL (n-1), ZBL (n-1)-WL (n+3), ZBL (n+3) are shown representatively. In the memory cell block, memory cells of 2 bits are coupled to the same bit line via one contact hole. Memory cells MC's aligned in the row direction are coupled either to a true bit line BL or to a complementary bit line ZBL.
Column select gates CSG's are placed alternately at both opposite sides of the memory cell block. Column select gates CSG (n-1)-CSG (n+3) include sense amplifier circuits, which in turn are disposed alternately for bit line pairs BLP's. Column select gates CSG (n)-CSG (n+3) are selected according to a column select signal on column select line CSL (1) to couple corresponding bit line pairs to local IO line pairs.
In FIG. 18, bit line pair BL (n) and ZBL (n) are connected to local IO lines LIO (0) and ZLIO (0), respectively, via column select gate CSG (n). Bit lines BL (n+2) and ZBL (n+2) are connected to local IO lines LIO (2) and ZLIO (2), respectively, via column select gate CSG (n+2). Bit lines BL (n+1) and ZBL (n+1) are connected to local IO lines LIO (1) and ZLIO (1), respectively, via column select gate CSG (n+1). Bit lines BL (n+3) and ZBL (n+3) are connected to local IO lines LIO (3) and ZLIO (3), respectively, via column select gate CSG (n+3). In local IO lines LIO (0)-LIO (3) and ZLIO (0)-ZLIO (3), one of paired local IO lines is placed between local IO lines another pair, because of the following reasons. If a pair of local IO lines LIO and ZLIO are disposed adjacent to each other, it would result in a stringent pitch condition for placing transfer gates included in the column select gates. To alleviate this pitch condition, adjacent local IO lines are connected to bit lines in different columns.
Local IO lines LIO (0) and ZLIO (0) are connected to global IO lines GIO (0) and ZGIO (0) via a block select gate BSG. Global IO lines GIO (1) and ZGIO (1) are connected via block select gate BSG to local IO lines LIO (1) and ZLIO (1), which in turn are placed, in the diagram, at the lower side of the memory cell block.
Local IO lines LIO (2) and ZLIO (2) are connected via block select gate BSG respectively to global IO lines GIO (2) and ZGIO (2), which in turn are placed at the right side in the diagram. Local IO lines LIO (3) and ZLIO (3) are connected to global IO lines GIO (3) and ZGIO (3). In global IO lines GIO and ZGIO, paired global IO lines are not disposed adjacent to each other, also to alleviate the pitch condition of the block select gates.
Therefore, global IO lines GIO (0), ZGIO (0), GIO (1) and ZGIO (1) placed at one side in a row direction of the memory cell block correspond to adjacent bit line pairs BL (n), ZBL (n), and BL (n+1), ZBL (n+1) of the memory cell block. Similarly, global IO lines GIO (2), GIO (3), ZGIO (2) and ZGIO (3) placed at the other side of the memory cell block correspond to adjacent bit lines BL (n+2), ZBL (n+2), BL (n+3) and ZBL (n+3) of the memory cell block.
In operation, when column select line CSL (1) is selected, four column select gates CSG (n)-CSG (n+3) are selected, and adjacent bit line pairs of 4 bits are connected to local IO line pairs LIO (0), ZLIO (0)-LIO (3), ZLIO (3), respectively. If word line WL (m) is selected, memory cells of 4 bits, MC (m, n), MC (m, n+1), MC (m, n+2), and MC (m, n+3) are selected. Data writing or reading is performed for the selected memory cells, via global IO line pair GIOP and local IO line pair LIOP.
FIG. 19 is a diagram schematically showing a configuration of a preamplifier+write driver block for global IO line pairs of 8 bits. In FIG. 19, write/read amplifiers RW0-RW7 are provided corresponding to pairs of global IO lines GIO (0), ZGIO (0)-GIO (7), ZGIO (7), respectively. Select circuits SW0-SW7 are provided corresponding to respective write/read amplifiers RW0-RW7. Four select circuits SW0-SW3 are provided with column select signals Y (A)-Y (D), respectively, and four select circuits SW4-SW7 are provided with column select signals Y (A)-Y (D), respectively. Select circuits SW0-SW7 are rendered conductive when a test mode designating signal (a compression test mode designating signal) TESTA is activated.
Select circuits SW0-SW3, when conductive, connect corresponding wlitehread amplifiers RW0-RW3 to internal data bus lines DB (0), ZDB (0). Select circuits SW4-SW7, when conductive, connect corresponding write/read amplifiers RW4-RW7 to internal data bus lines DB (1), ZDB (1). Internal data bus lines DB (0), ZDB (0) and DB (1), ZDB (1) are coupled to external data terminals DQ0 and DQ1, respectively (via an input/output circuit).
In a normal operation mode, one out of 4 bits of column select signals Y (A)-Y (D) is driven to a selected state. Therefore, one of four select circuits SW0-SW3 is rendered conductive, and one of four write/read amplifiers RW0-RW3 is coupled to internal data lines DB (0), ZDB (0). One of select circuits SW4-SW7 is also rendered conductive, and one of wiite/read amplifiers RW4-RW7 is connected to internal data lines DB (1), ZDB (1). Thus, data wiiting/reading is performed for global IO line pairs of 2 bits out of 8 bits of global IO line pairs.
In a test operation mode, select circuits SW0-SW7 are all rendered conductive. Write/read amplifiers RW0-RW3 are connected, in parallel, to internal data lines DB (0), ZDB (0), and wlite/read amplifiers RW4-RW7 are also connected to internal data lines DB (1), ZDB (1) in parallel. The write/read amplifiers or the global data line pairs connected to the same internal data bus line pair are coupled with the memory cells selected by the same column select line. For determination of match/mismatch of data for these memory cells of 4 bits, the 4-bit data can be compressed to 1bit data to determine pass/fail of the memory cells of 4 bits.
FIG. 20 is a diagram showing in more detail the configuration of the wlite/read amplifier and the select circuit shown in FIG. 19. In FIG. 20, the configurations of wiite/read amplifier RW1 and select circuit SW1 provided for global IO lines GIO (1) and ZGIO (1) are representatively shown.
Referning to FIG. 20, write/read amplifier RW1 includes: a write amplifier (write driver) WA for amplifying received data for transmission to global IO lines GIO (1) and ZGIO (1); and a read amplifier (preamplifier) RA for amplifying, when activated, complementary data signals applied onto global IO lines GIO (1) and ZGIO (1). Write amplifier WA is set at an output high impedance state when inactivated. These write amplifier WA and read amplifier RA are activated by an activation signal that is not specifically shown.
Select circuit SW1 includes: an OR/NAND composite gate G1 receiving a write designating signal WDE, test mode designating signal TESTA and column select signal Y (B); a select gate SG1 rendered conductive according to an output signal of OR/NAND composite gate G1 for coupling internal data lines DB (0)and ZDB (0) to write amplifier WA; an inverter G2 receiving test mode designating signal TESTA; an NAND gate G3 receiving an output signal of inverter G2, column select signal Y (B) and a read designating signal RDE; a select gate SG2 rendered conductive according to an output signal of NAND gate G3 for transmitting the output signal of read amplifier RA to internal data lines DB (0) and ZDB (0); an NAND gate G4 receiving the output signal of read amplifier RA, test mode designating signal TESTA and read designating signal RDE; a NAND gate G5 receiving a complementary output signal of read amplifier RA, test mode designating signal TESTA and read designating signal RDE; a drive transistor PG1 for driving internal data line DB (0) to an H level according to an output signal of NAND gate G4; and a drive transistor PG2 for driving complementary internal data line ZDB (0) to an H level according to an output signal of NAND gate G5.
OR/NAND composite gate G1 is equivalent to a configuration including an OR gate receiving test mode designating signal TESTA and column select signal Y (B), and a NAND gate receiving an output signal of the OR gate and write designating signal WDE.
In a normal operation mode, test mode designating signal TESTA is at an L level of an inactive state, output signals of NAND gates G4 and G5 are fixed at an H level, and diive transistors PG1 and PG2 keep an off state. With such a condition, in data writing, column select signal Y (B) and write designating signal WDE both attain an H level of an active state. The output signal of OR/NAND gate G1 then goes to an L level, select gate SG1 is rendered conductive, and complementary data on internal data lines DB (0) and ZDB (0) are transmitted to write amplifier WA. Write amplifier WA is activated according to a write driver enable signal (not shown) that is activated in response to write designating signal WDE, and amplifies the complementary data received from internal data line pair DB0 and transmits the amplified data to global IO lines GIO (1) and ZGIO (1).
Similarly, in data reading, column select signal Y (B) and read designating signal RDE both attain an H level of a selected state. The output signal of NAND gate G3 goes to an L level, and complementary data amplified by read amplifier RA are transmitted onto internal data line pair DB0.
In a test mode, test mode designating signal TESTA is driven to an H level of a selected state. The output signal of inverter G2 attains an L level, the output signal of NAND gate G3 is set to an H level, and select gate SG2 keeps a nonconductive state. In data writing, the output signal of OR/NAND composite gate G1 attains an L level in response to activation of write designating signal WDE, select gate SG1 is rendered conductive, and complementary data on data line pair DB0 are transmitted to write amplifier WA The logic level of column select signal Y (B) is disregarded in this test mode operation. Therefore, as shown in FIG. 19, write amplifiers WA of 4 bits connected to one data line pair receive the same data. In other words, select circuits SW0-SW7 in FIG. 19 are all rendered conductive. Thus, internal data lines DB (0), ZDB (0) are connected to write/read amplifiers RW0-RW3, and internal data lines DB (1), ZDB (1) are commonly coupled to write/read amplifiers RW4-RW7. Accordingly, the same data are written into memory cells of 4 bits selected by one column select line.
In data reading, when read designating signal RDE attains an H level, one of NAND gates, G4 or G5, which has received H level data from read amplifier RA outputs a signal of an L level. One of the drive transistors, PG1 or PG2, is thus rendered conductive, and one of the internal data lines, DB (0) or ZDB (0), is driven to an H level. The same data have been written into memory cells coupled to the same internal data line pair. If the H level data have been written therein, internal data line DB (0) is driven to an H level, and internal data line ZDB (0) is held at an L level (here, in the test mode, internal data lines DB (0) and ZDB (0) are precharged to the L level before data reading). In the case where there exists a defective memory cell in the memory cells of 4 bits selected by one column select line, reverse data are output from read amplifier RA. Thus, in this case, internal data lines DB (0) and ZDB (0) are both driven to the H level, or the reverse data of the write data are output (if all the bits are defective). The presence of a defect in the memory cells of 4 bits can be detected by comparing a signal on internal data line pair DB0 with an expected value.
In the IO compression test mode, data of the memory cells of 4 bits have been compressed to data of 1 bit, and the memory cells of 4 bits can be tested at one time. This can prevent the time required for the test from increasing even when the storage capacity of the semiconductor memory device increases.
FIG. 21 is a diagram schematically showing connection between selected memory cells and data terminals in the IO compression test mode in a conventional semiconductor memory device. Referring to FIG. 21, a data terminal DQ of 1 bit is coupled to internal data line pair DB. In the IO compression test mode, this internal data line pair DB is coupled to four global IO line pairs GIOa-GIOd. These global IO line pairs of 4 bits, GIOa-GIOd, are coupled via block select gates to local IO line pairs LIOa-LIOd, respectively. Local IO line pairs LIOa-LIOd are connected via column select gates CSG to memory cells MCa-MCd, respectively.
These memory cells of 4 bits, MCa-MCd, are selected simultaneously according to a column select signal on the same column select line CSL. Therefore, data applied to data terminal DQ are written into all 4 bits of these memory cells MCa-MCd. The data at the same logic level are also transmitted onto global IO line pairs GIOa-GIOd and local IO line pairs LIOa-LIOd. Accordingly, it is impossible to detect defects such as short circuits between global IO lines, between local IO lines or between adjacent memory cells. This is because the data at the same logic level are transmitted, and this logic level will not change even if a short circuit takes place.
A test decision circuit TDK simply compares data appeared on internal data line pair DB with an expected value and, according to their match/mismatch, detects the presence/absence of defects in the memory cells of 4 bits, or it only buffers read data for output to an outside. Therefore, in the array configuration shown in FIG. 18, for example, it is impossible to detect a short circuit of memory cells MC (m, n) and MC (m, n+1), or detect an effect of interference between the adjacent bit lines. Even if an IO compression test mode is utilized to shorten the test time, the test contents are limited. With the compression test mode, interference between bit lines, a short circuit of global IO lines, a short circuit of local IO lines or a short circuit between memory cells cannot be detected, and therefore, it is impossible to realize a precise test.